PCIe generation and lane count are two separate parts of the bandwidth label
A storage listing such as “PCIe 4.0 x4” combines two facts: the signaling generation and the number of PCI Express lanes assigned to the link. A newer generation raises the rate per lane; a wider link adds more lanes. Neither label guarantees that an SSD will sustain the interface ceiling in real file transfers.
Start with the label: generation × lane count
PCI Express links are built from lanes. PCI-SIG's PCIe 5.0 FAQ lists links with 1, 2, 4, 8, 12, 16, or 32 lanes, all operating at a supported signaling rate. Consumer NVMe M.2 SSDs commonly use a four-lane PCIe path, which is why product specifications often say x4.
The generation tells you the maximum signaling rate available per lane. The lane count tells you how many of those lanes are combined in parallel. So “PCIe 5.0 x4” is not one indivisible version name; it means a PCIe 5.0-rate link using four lanes.
| Consumer-relevant link | Raw signaling rate per lane | Encoding used by these generations | Approx. theoretical bandwidth per direction |
|---|---|---|---|
| PCIe 3.0 x4 | 8.0 GT/s | 128b/130b | 3.94 GB/s |
| PCIe 4.0 x4 | 16.0 GT/s | 128b/130b | 7.88 GB/s |
| PCIe 5.0 x4 | 32.0 GT/s | 128b/130b | 15.75 GB/s |
The approximate GB/s figures above are derived from PCI-SIG's published signaling rates and the 128b/130b encoding relationship. They are transport ceilings after line encoding, not benchmark promises.
GT/s is not the same unit as GB/s
GT/s means giga-transfers per second. It describes signaling events on a lane. GB/s means gigabytes per second. Converting from one to the other requires knowing how the link encodes useful bits into those transfers.
PCI-SIG explains that PCIe 3.0 moved away from the older 8b/10b scheme and uses a much more efficient 128b/130b encoding. In simplified arithmetic, 128 useful encoded bits are carried within 130 transmitted bits at that line-encoding layer.
For PCIe 4.0 x4, the transparent calculation is:
Why each generation roughly doubles the x4 ceiling
PCI-SIG states that PCIe 4.0 uses a 16.0 GT/s bit rate and doubles the bandwidth of PCIe 3.0. PCIe 5.0 doubles the signaling rate again to 32.0 GT/s per lane. Because PCIe 3.0, 4.0 and 5.0 use the same high-efficiency 128b/130b encoding family, doubling the per-lane signaling rate approximately doubles the encoded link bandwidth when the lane count stays the same.
That is why the progression for an x4 link is roughly 3.94 → 7.88 → 15.75 GB/s per direction. The math is regular; actual SSD performance is not.
An SSD advertised at 7,000 MB/s is not “using all 8 GB/s”
A PCIe 4.0 x4 interface has an encoded link ceiling near 7.88 GB/s, but a storage benchmark measures useful data moved by a specific SSD under a specific workload. PCIe packets, NVMe commands, controller behavior, NAND flash, firmware, queue depth, temperature, cache state and benchmark methodology all sit between the link ceiling and the reported application result.
A drive advertised around 7,000 MB/s sequential read can therefore be operating close to the practical upper region of PCIe 4.0 x4 without contradicting the larger theoretical link number. The missing bandwidth is not necessarily “wasted”; the measurements describe different layers.
The same distinction applies to PCIe 5.0 SSDs. A 15.75 GB/s encoded x4 ceiling does not mean every Gen5 drive should benchmark at 15.75 GB/s. The interface makes that transport capacity possible; the storage device still has to supply data fast enough to use it.
x4, x2 and x1 can matter as much as the generation
A newer generation with fewer lanes can have a similar transport ceiling to an older generation with more lanes. For example, PCIe 4.0 x2 has the same raw lane-rate total as PCIe 3.0 x4 before considering the shared 128b/130b encoding: 16 GT/s × 2 lanes versus 8 GT/s × 4 lanes.
This is why a motherboard manual that says only “PCIe 4.0” is incomplete for storage performance. The slot's actual lane allocation matters. An M.2 connector can also share platform lanes or operate with a narrower link depending on the system design.
| Example link | Approx. encoded ceiling per direction | What it illustrates |
|---|---|---|
| PCIe 3.0 x4 | 3.94 GB/s | Older generation, four lanes |
| PCIe 4.0 x2 | 3.94 GB/s | Newer generation can offset fewer lanes |
| PCIe 4.0 x4 | 7.88 GB/s | Four lanes at double the Gen3 rate |
| PCIe 5.0 x2 | 7.88 GB/s | Again, double the per-lane rate with half the lanes |
| PCIe 5.0 x4 | 15.75 GB/s | Four lanes at the Gen5 rate |
Backward compatibility does not preserve the faster speed
PCI Express generations are designed for backward compatibility. PCI-SIG's PCIe 6.0 guidance explicitly states that PCIe 6.0 products maintain backward compatibility with previous generations, continuing a long-standing PCIe design principle.
Compatibility does not mean the older endpoint suddenly gains the newer rate. If a PCIe 5.0-capable SSD is connected through a host path that only supports PCIe 4.0, the useful link is constrained to the mutually supported configuration. Lane count can constrain it too: a device capable of x4 cannot force a host connection that only provides x2 to become x4.
For upgrades, this is usually good news: a newer SSD may work in an older compatible slot. It is not a reason to assume the drive will reach the speed printed on its box.
M.2 does not tell you the PCIe generation or lane count
M.2 is a form-factor family. It does not itself promise PCIe 3.0, 4.0, 5.0, four lanes, NVMe, or even PCIe storage at all. The separate M.2 versus NVMe versus SATA guide explains why physical format and storage protocol must be checked independently.
When the slot is PCIe/NVMe-capable, the next questions are the supported generation and the number of lanes assigned to that slot. Those details normally come from the motherboard, laptop or device manual rather than from the physical connector.
A buying workflow for an NVMe SSD upgrade
- Confirm the slot supports PCIe/NVMe storage. Do not infer this from M.2 shape alone.
- Find the slot's maximum PCIe generation. Record Gen3, Gen4, Gen5 or the exact wording used by the manufacturer.
- Find the lane width. Look for x4, x2 or another explicit lane allocation.
- Check whether lanes are shared. Some platforms change slot behavior when other storage or expansion devices are populated.
- Compare the SSD's interface capability with the host ceiling. A faster drive can be compatible while operating below its own maximum.
- Then compare measured workloads. Sequential headline speed is only one SSD behavior; sustained writes, random I/O, thermals, capacity and endurance can matter more for a specific use.
Why PCIe 6.0 and 7.0 are not included in the simple calculator table
PCI-SIG's current approved base specification is PCI Express 7.0, dated 11 June 2025, and PCIe 6.0 introduced a major signaling and framing change: 64.0 GT/s PAM4, Forward Error Correction and Flit-based operation. PCIe 7.0 continues the PAM4/Flit era at a higher rate.
That makes a single “multiply GT/s by 128/130” shortcut inappropriate once the discussion moves beyond PCIe 5.0. This page deliberately keeps its consumer SSD arithmetic to PCIe 3.0–5.0, where the same 128b/130b relationship makes the generation-and-lane comparison transparent.
Primary sources
- PCI-SIG — PCIe 5.0 bit rates and lane widths, for supported lane counts and the 32.0 GT/s Gen5 rate.
- PCI-SIG — PCIe 4.0 bit rate, for the 16.0 GT/s Gen4 rate and doubled-bandwidth context.
- PCI-SIG — PCIe 3.0 encoding and bandwidth explanation, for the move to 128b/130b encoding and the 8.0 GT/s Gen3 relationship.
- PCI-SIG — PCI Express 6.0 Specification, for the 64.0 GT/s PAM4/Flit transition and backward-compatibility context.
- PCI-SIG — PCI Express Base specifications, for the currently approved PCIe base-revision history.
Bottom line
Read a PCIe storage label in two dimensions: generation sets the per-lane signaling rate, while x1/x2/x4 sets how many lanes participate. For common NVMe x4 links, PCIe 3.0, 4.0 and 5.0 provide approximate encoded one-direction ceilings of 3.94, 7.88 and 15.75 GB/s respectively. Those are interface ceilings, not guaranteed SSD benchmark results.